<p>My goal is to consolidate a research group in embedded systems' engineering that fosters authenticity, autonomy, curiosity, and the desire to learn. I'm committed to providing a space that encourages each person to express their unique perspectives and embrace new ideas. We'll strive to reach the highest level of understanding in embedded systems engineering and build tools, concepts, and knowledge that are recognized in top-level venues, industrial collaborations, and open source projects. Join me in creating a productive and supportive environment that drives innovation!</p>


Proceedings of the 2024 10th International Conference on Computer Technology Applications

Layer-wise Exploration of a Neural Processing Unit Compiler's Optimization Space

IEEE Internet of Things Journal

ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems

ACM Transactions on Embedded Computing Systems (TECS)

Interruptible Remote Attestation of Low-End IoT Microcontrollers via Performance Counters

Proceedings of COSADE 2023: Constructive Side-Channel Analysis and Secure Design

Efficient Attack-Surface Exploration for Electromagnetic Fault Injection

ArXiv (also in IACR ePrint)

The propagation game: on simulatability, correlation matrices, and probing security

Proceedings of DATE 2022: International Conference on Design, Automation and Test in Europe

ADD-based Spectral Analysis of Probing Security

IET Information Security

On robust strong‐non‐interferent low‐latency multiplications

Journal of Cryptographic Engineering

A relation calculus for reasoning about t-probing security

IEEE Transactions on Computer Aided Design of Integrated Circuits

DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling

IACR

An F-algebra for analysing information leaks in the presence of glitches

Proceedings of FDTC 2018: Workshop on Fault Diagnosis and Tolerance in Cryptography

Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light

Proceedings of the 1st International Workshop on Software Engineering for Cognitive Services

Toward Truly Personal Chatbots: On the Development of Custom Conversational Assistants

Proceedings of DATE 2015: International Conference on Design, Automation and Test in Europe

Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints

IEEE Transactions on Computers

Spectral features of higher-order side-channel countermeasures

Proceedings of CAISE 2018: Conference on Advanced Information Systems Engineering

Context-Aware Access to Heterogeneous Resources Through On-the-Fly Mashups

ACM Transactions on Design Automation of Electronic Systems (TODAES)

CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks

Symbolic analysis of higher-order side channel countermeasures

Proceedings of RMC 2016: Rapid Mashup Development Tools, Revised Selected Papers

On the Role of Context in the Design of Mobile Mashups

SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis

IACR Transactions on Cryptographic Hardware and Embedded Systems

On the spectral features of robust probing security

Proceedings of SAMOS 2014: XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Combining application adaptivity and system-wide Resource Management on multi-core platforms

Proceedings of ISPA 2014: IEEE International Symposium on Parallel and Distributed Processing with Applications

OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms

Proceedings of ASAP 2014: IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications

Proceedings of ARC 2014: Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium

Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures

Proceedings of FPL 2013: International Conference on Field Programmable Logic and Applications

Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction

Proceedings of DATE 2014: International Conference on Design, Automation and Test in Europe

DeSpErate: Speeding-up Design Space Exploration by using Predictive Simulation Scheduling

Conference on Advanced Topics and Auto Tuning in High Performance Scientific Computing (HPSC) - Taipei, Taiwan - March 27-29, 2013

Keynote: Principles of Design Space Exploration in the Embedded Multi-core Era

IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, ESTIMedia 2012, Tampere, Finland, October 11-12, 2012

Keynote: Design space exploration and run-time resource management in the embedded multi-core era

Proceedings of INA-OCMC 2012: Interconnection Network Architecture: On-Chip, Multi-Chip

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach

Proceedings of VLSI-SoC 2013: International Conference on Very Large Scale Integration and System-on-Chip

A Framework for Compiler Level Statistical Analysis over Customized VLIW Architecture

Parallel Computing

ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models

Proceedings of CODES+ISSS 2012: International Conference on Hardware/Software codesign and System Synthesis

An Exploration Methodology for a Customizable OpenCL Stereo-Matching Application Targeted to an Industrial Multi-Cluster Architecture

Proceedings of DATE 2013: International Conference on Design, Automation and Test in Europe

Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models

A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization

Design Space Exploration and Run-time Resource Management for Multi-cores

US 7243213

Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product

US 6889317

Processor architecture

Proceedings of ReCoSoC 2011: Reconfigurable Communication-centric Systems-on-Chip

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach

Proceedings of the ARCS Workshops 2012

Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework

Journal of the Royal Society of Medicine

How might the iPad change healthcare?

An Instruction-Level Energy Model for Embedded VLIW Architectures

Proceedings of DATE 2003 Designers Forum: IEEE Design, Automation and Test Conference in Europe

Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture

Proceedings of NoCArc 2011: 4th International Workshop on Network on Chip Architectures

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip

Proceedings of INDIN 2011: IEEE Conference on Industrial Informatics

Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: 2PARMA Approach

Lecture Notes in Electrical Engineering, Vol. 57 - Selected Papers from VLSI 2010 Annual Symposium, N. Voros et al. (Eds.)

MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures

Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, Cristina Silvano, William Fornaciari, Eugenio Villar (Eds.)

Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming

Design Space Exploration of Parallel Architectures

Design Space Exploration Supporting Run-Time Resource Management

Response Surface Modeling for Design Space Exploration of Embedded Systems

Optimization Algorithms for Design Space Exploration of Embedded Systems

The MULTICUBE Design Flow

Proceedings of SASP 2011: IEEE Symposium on Application Specific Processors

ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems

Computers Digital Techniques, IET

Linking run-time resource management of embedded multi-core platforms with automated design-time exploration

ACM Transactions in Embedded Computing Systems

A Variability-Aware Robust Design Space Exploration Methodology for on-Chip Multiprocessors Subject to Application Specific Constraints

Proceedings of ISVLSI 2010: IEEE Annual Symposium on VLSI

Proceedings of DAC 2010: Design Automation Conference

A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip

Proceedings of 2PARMA: Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures

Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors

Proceedings of DATE 2010: IEEE Design, Automation and Test Conference in Europe

Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions

An industrial design space exploration framework for supporting run-time resource management on multi-core systems

Proceedings of NoCArc '09: International Workshop on Network on Chip Architectures

Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips

ReSPIR: A Response Surface-based Pareto Iterative Refinement for Application-Specific Design Space Exploration

Proceedings of IEEE Symposium on Application Specific Processors 2009

A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip

Proceedings of Euromicro Conference on Digital System Design (DSD)

Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip

Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation

Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques

Proceedings of RAPIDO 2009: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

A DoE/RSM-based Strategy for an Efficient Design Space Exploration targeted to CMPs

Proceedings of IEEE/ACM ASPDAC 2009: Asia and South Pacific Design Automation Conference

Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures

Workshop on Streaming Systems: From Web and Enterprise to Multicore (in conjunction with IEEE/ACM Micro-41)

Data Flow Deadlock Avoidance for Streaming Applications Mapped on Network-on-Chips

Proceedings of ESTIMEDIA 2008: IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

Robust Optimization of SoC Architectures: A Multi-Scenario Approach

Proceedings of IFIP VLSI-SOC 2008: International Conference on Very Large Scale Integration

An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks

Proceedings of DSD 2008: IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools

Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration

Proceedings of IC-SAMOS 2008: International Conference on Embedded Computer Systems Architectures, Modeling and Simulation

An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods

Proceedings of SASP 2008: IEEE Symposium on Application Specific Processors

An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints

Design Automation for Embedded Systems

Reducing the Complexity of Instruction-Level Power Models for VLIW Processors

New Trends in Cryptographic Systems, N. Nedjah and L.M. Mourelle (Eds.)

A Power Attack Methodology to AES Based on Induced Cache Misses: Procedure, Evaluation and Possible Countermeasures

Proceedings of PATMOS 2001: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation

A Power Modeling and Estimation Framework for VLIW-based Embedded Systems

Proceedings of DATE 2004: IEEE Design, Automation and Test Conference in Europe

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip

Proceedings of DAC 2002: Design Automation Conference

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Proceedings of CODES-2000: 8th ACM/IEEE International Workshop on Hardware/Software Co-Design

Instruction-Level Power Estimation for Embedded VLIW Cores

Proceedings of ITCC 2005: International conference on Information Technology

AES Power Attack Based on Induced Cache Miss and Countermeasure

Journal of Embedded Computing

Multi-Objective Design Space Exploration of Embedded Systems

Proceedings of CODES 2001: 9th ACM/IEEE International Symposium on Hardware/Software Co-Design

A Design Framework to Efficiently Explore Energy-Delay Tradeoffs

Integration, The VLSI Journal

Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach

Proceedings of GLSVLSI 2004: Great Lakes Symposium on VLSI

Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors

Ultra Low-Power Electronics and Design, E. Macii (ed.)

Proceedings of PATMOS 2004: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation

Low Effort, High Accuracy Network-on-Chip Power Macro Modeling

Proceedings of PATMOS 2003: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation

A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems

Proceedings of ISCAS 2003: IEEE Int. Symposium on Circuits and Systems

About the performance of the advanced encryption standard in embedded systems with cache memory

Proceedings of GLSVLSI 2003: Great Lakes Symposium on VLSI

A System-Level Methodology for Fast Multi-Objective Design Space Exploration

Branch Prediction Techniques for Low-Power VLIW Processors

Technical report

Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems

Proceedings of DATE 2012: IEEE Design, Automation and Test Conference in Europe

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

Proceedings of SAC 2003: Symposium on Applied Computing

A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems

OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces

Proceedings of ICCAD-2000: IEEE/ACM Int. Conference on Computer Aided Design

Power Exploration for Embedded VLIW Architectures

A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-Power Data Forwarding for VLIW Embedded Architectures

Proceedings of DATE 2002: IEEE Design, Automation and Test Conference in Europe

An instruction-level methodology for power estimation and optimization of embedded VLIW cores

Research