I am an associate professor at Politecnico di Milano and I have worked
in processor architecture research and development for one of the top
semiconductor companies in the world. My background is rooted in modeling
and simulation of digital systems although I have expanded my interests
to functional programming and domain specific languages.
In 2016 I've helped introduce some novel theoretical results
in the field of cryptography and (in 2015 and 2017) I've been awarded
with several grants from industrial partners for devising a reliable
design methodology for cryptographic circuits. 


Vittorio Zaccaria

Welcome to my website.
I am an associate professor at Politecnico di Milano and I have worked
in embedded processor architecture R&D for one of the top
semiconductor companies in the world.

My group is currently working on topics 
related to embedded systems (hardware and software), 
security, cryptography, operating systems. If you
are inclined to work on these topics feel free to get in touch for a
possible collaboration or a thesis.


for the exceptional contribution to the state of the art of research in processor architecture.

Dimitris N. Chorafas Award

as a co-author of 'A Correlation-Based Design Space Exploration Methodology for Multiprocessor Systems-on-Chip' published at DAC 2010.

HiPEAC Award

for creating a valuable opportunity for product commercialization of research results.

Idea2Product, 2nd runner up

Electronics

Electronics - Special Issue on Operating Systems and Hardware Security

PARMA-DITAM Workshop

COMPSAC (SEPT)

COSADE

DITAM Workshop

ADAPT Workshop

PARMA Workshop (co-located with ARCS)

NoCArc Workshop

Trust Workshop

Micro Conference

DATE Conference - Track A8 (Multi-Core Platforms)

This project started from an actual industrial need, i.e., providing
the designer of cryptographic algorithms with guidelines and tools
that make it possible to implement and validate the primitive while
assessing the desired level of protection.

The problems with existing methods and tools that brought us to seek
new approaches are just a few; first, high level
specification/prototyping of the algorithm is decoupled from low level
implementation. This brings a host of issues, among which the fact
that manual translation can introduce subtle bugs and unanticipated
behavior. Besides this, the specification is usually done in weakly
typed languages, bringing additional source of unexpected behavior,
test and refactoring complexity.

My main goal is to investigate how a strongly typed functional
programming language could be used to build a DSLs to synthesize these
kind of algorithms in hardware, by bridging the gap between spec and
implementation with automatic tools.


Countermeasures against side-channel attacks

In 2014 I realized that my computer science class was undergoing a
major challenge. The number of students was becoming huge and resource
assignment from my university (in terms of teaching assistants funded
by the university) was on a decreasing trend. In fact, the ratio
between qualified teaching assistants (those who have a degree in
computer engineering) and students had fallen below 1/100, making it
hard to bring students to complete even the simplest hands-on lab. I
always had the ambition to not leave anyone behind so I gradually
started to study the current MOOC technologies to see whether they
could be used to keep the students on track.

Currently, I am creating the first online course that is meant to
complement the face to face lectures that I give. The course can be
edited collaboratively by teachers (on Github) through a YAML based
format that I designed; it can then be imported into an EDX server to
be used by the students who can submit their homework to an automatic
grader that I wrote using containerization technology.


Techniques to support teaching to a massive amount of students

Since 1999, I have been interested into estimating and optimizing
the power consumption of microprocessors and microprocessor-based
systems.


Power estimation and optimization of processor-based systems

During my 4 years stint in the industry, I have worked on
a variety of projects related to exploiting task level parallelism.
I have had the opportunity to work within an international team
on the entire stack of hardware and software design tools for
an embedded processor.


Task Level Parallelism

Edoardo Paone

Giovanni Mariani

Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product

Processor architecture

ISC HPC

IEEE Embedded Systems Letters

Design Automation for Embedded Systems

IEEE Transactions on Computers

IEEE Transactions on Dependable and Secure Computing

Concurrency and Computation: Practice and Experience

IEEE Transactions on Emerging Topics in Computing

Transactions on Embedded Computing Systems

IEEE Transactions on Very Large Scale Integration Systems

Journal of Low Power Electronics JOLPE

Transactions on Parallel and Distributed Systems

Design Automation Conference

Maria Chiara Molteni

Politecnico di Milano

STMicroelectronics

Offis e.V

GMV Aerospace and Defence SA

Cobra

EUROTECH Group S.p.A.

Intecs SpA

iXtronics GmbH

EDALab s.r.l.

DOCEA Power

Politecnico di Torino

University of Cantabria

KTH (Royal Institute of Technology)

The European Electronic Chips and Systems design Initiative

ST-PoliTo s.c.a.r.l.

Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties (CONTREX)

Thales Communications SA

Synopsys Belgium NV

ChipVision Design Systems AG

EDALab srl

Magillem Design Services SAS

Universidad de Cantabria

Interuniversitair Micro-Electronica Centrum vzw

CO-design and Power Management in PLatform-based Design Space EXploration (COMPLEX)

Fraunhofer Institute for Telecommunications Heinrich Hertz Institute (HHI)

Institute of Communication and Computer Systems

Rheinisch-Westfaelische Technische Hochschule Aachen

Synopsys

PARallel PAradigms and Run-time MAnagement techniques for Many-core Architectures

Imec

Esteco

ALaRI

Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications

Matteo Cairoli

Lorenzo Sanvito

Dario Cressoni

Alessandro Macchi

Andrea Masi

Dario Messina

Alessandro Borgonovo

Panzeri Ruggero

Joan Bushi

Subject: A new secure channel protocol based on sponge functions

Davide Grazioli

Subject: Implementation of PQC signatures using sponge functions

Matteo Carrara

Subject: A DSL language for chip assembly

Francesco Aristei

Subject: Extension of OsNoise hardware tracing to virtualised guests

Edoardo Poggi

Subject: Design space exploration of automotive systems' memory management units

Giorgio Maria Grandi

Subject: Security in automotive NoCs

Davide Pozzi

Subject: Automotive functional safety libraries

Daniele Carta

Efficient attack-surface exploration for electromagnetic fault injection

Andrea Aspesi

ConceptOS: a micro-kernel approach to over-the-air firmware updates on resource constrained IoT systems

Giuseppe Manzoni

An Analysis of Random Probing Security Properties in Masked Cryptographic Circuits

Davide Li Calsi

Interruptible Remote Attestation via Performance Counters

Alessandro Elio Cantini

Progetto e valutazione di una rete neurale eseguita su un sistema embedded a bassa potenza

Marco Redaelli

(provisional): A side channel attack methodology

Nicola Castaldo

A conceptual modeling approach for the rapid development of chatbots for conversational data exploration

Stefano Gianelli and Valerio Cassani

Progettazione di mashup per dispositivi mobili un metodo basato sulla modellazione di contesto

Stefano Lucchi and Davide Fava

Mash-up based service and data integration in the CAMUS framework

Lorenzo Delledonne

A methodology based on functional languages for the design of hardware cryptographic primitives resistant to side-channel attacks

Simone Borgio and Davide Bosisio

OpenStreamC - a development framework for streaming applications

Zhong Yi Hu

Power modeling of Networks-on-chip

Fabrizio Lucini

Specification and design of a prefetch unit for translating code at run-time

Simone Valsecchi

An algorithm for the efficient exploration of the architectural design space for microprocessor-based systems

Gianluca Palermo

A methodology for architectural exploration and information encoding for low-power digital systems

Alessandro Molgora and Claudio Lozza

Low-power state encoding techniques for finite state machines

Marco Gavazzi

Low-power VLIW re-scheduling algorithms

Lorenzo Salvemini

An architectural exploration methodology for low-power digital systems

Andrea Bona

A design of experiments methodology in a power estimation flow for VLIW processors

TII Cryptoseminar

An F-algebra for analysing information leaks in the presence of glitches

ESTIMEDA Workshop

Design space exploration and run-time resource management in the embedded multi-core era

HPSC Conference

Principles of Design Space Exploration in the Embedded Multi-core Era

Platform 2012 / STHORM Workshop

An Exploration Methodology for a Customizable OpenCL Stereo-Matching Application Targeted to P2012

RMC Challenge

On the Role of Context in the Design of Mobile Mashups

SASP Symposium

An efficient design space exploration methodology for on-chip multiprocessors subject to application-specific constraints

CODES 2001 Symposium

A Design Framework to Efficiently Explore Energy-Delay Tradeoffs

DAC Conference

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

ISCAS Conference

Fast system-level exploration of memory architectures driven by energy-delay metrics

 Here is the talk I gave about my research interests in computer modeling and architecture, focusing on the lessons I've learnt along the way.

Past and current research

The video we presented at the Design Automation Conference on June 2012.

DAC 2012 University Booth

Wrapping up the work done in the 2PARMA project.

2PARMA Project: a success story

A language for designing hardware countermeasures against side channel attacks. 
It is based on a final tagless approach for embedding domain specific languages. 


CASCA

An experiment in MOOC for my students of Informatica B. It allows to learn
a Matlab-like language through a set of small lectures and 
automatically graded exercises. It uses the EDX stack.


Polimi at Home (PAH)

Integration of various technologies from different project partners to create
a video-analytics application. 


2PARMA Use case n. 6

Architectural exploration framework retargetable to different processor-based 
architectures and exploration algorithms. The tool contains also advanced algorithms 
for DoE generation and response surface modeling. 


Multicube Explorer

Development toolchain for applications based on the stream oriented programming 
model.


xSTreamC compiler and nSTream simulator

Production-grade instruction set simulator for the ST200 VLIW processor family 
(functional and timing behavior models). Kernel, device components, 
cache-coherency, secure-storage, co-hosting


ST200-ISS

Tools for run-time power estimation of STBus proprietary bus 
technology (C/SystemC). These tools are currently part of the internal STBus 
product work-flow


STBus Power estimation

General software design

General hardware design

Artificial languages

Processor architecture design

Embedded Systems Design

Proceedings of the 2024 10th International Conference on Computer Technology Applications

Layer-wise Exploration of a Neural Processing Unit Compiler's Optimization Space

IEEE Internet of Things Journal

ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems

ACM Transactions on Embedded Computing Systems (TECS)

Interruptible Remote Attestation of Low-End IoT Microcontrollers via Performance Counters

Proceedings of COSADE 2023: Constructive Side-Channel Analysis and Secure Design

Efficient Attack-Surface Exploration for Electromagnetic Fault Injection

ArXiv (also in IACR ePrint)

The propagation game: on simulatability, correlation matrices, and probing security

Proceedings of DATE 2022: International Conference on Design, Automation and Test in Europe

ADD-based Spectral Analysis of Probing Security

IET Information Security

On robust strong‐non‐interferent low‐latency multiplications

Journal of Cryptographic Engineering

A relation calculus for reasoning about t-probing security

IEEE Transactions on Computer Aided Design of Integrated Circuits

DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling

IACR

Vittorio Zaccaria

Associate professor @ Politecnico di Milano, Italy

Latest publications